1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming transistor devices that use high-k insulating materials and the resulting devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET (whether an NFET or a PFET) is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Electrical contacts are made to the source and drain regions, and current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If there is no voltage applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region. Traditionally, FETs have been substantially planar devices, but similar principles of operation apply to more three-dimensional FET structures, devices that are typically referred to as FinFETs.
For many early device technology generations, the gate electrode structures of most transistor elements have been comprised of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate electrode stacks comprising alternative materials in an effort to avoid the short-channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 14-32 nm, gate stacks comprising a so-called high-k dielectric/metal gate (HK/MG) configuration have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations.
As noted above, many current day advanced integrated circuit products use transistor devices that have a high-k dielectric/metal gate (HK/MG) configuration to reduce device leakage and to increase device performance. However, the benefits achieved using such a high-k dielectric/metal gate (HK/MG) configuration for certain transistors have not been effectively realized. For example, in some integrated circuit products, some of the transistor devices are exposed to a larger operating voltage than other transistor devices on the same integrated circuit product. One specific example would be that of transistors that are employed in I/O circuitry, which may be exposed to an operating voltage of about 1.8 volts, whereas transistors that are part of the logic circuitry of such an integrated circuit product may only be exposed to a relatively lower operating voltage, e.g., about 1.0 volts. To accommodate these different voltage levels, prior art techniques involved integration of silicon dioxide layers with different thicknesses being appropriate to fulfill specific supply voltage dependent gate leakage and reliability requirements. For example, one such integration technique, generally referred to as a dual gate oxide process, uses the term “core” for areas with a relatively thin gate dielectric, and the term “IO” for areas with relatively thick gate dielectric layers. Such a dual gate oxide process typically involves forming (by deposition or thermal growth) a relatively thick (typically above 2 nm) type 1 oxide, masked oxide removal over the core area by wet etching and blanket growth, as well as several treatments of thin (typically below 1 nm) type 2 oxide followed by polysilicon deposition. It is relatively straightforward to produce a relatively homogeneous thick gate oxide for devices with a traditional gate structure (e.g., silicon dioxide gate insulation layer and polysilicon gate electrode) because the electrical and reliability specific properties of such layers are scaled with the total thickness. However, the situation is different for devices that employ a high-k gate insulation layer and one or more metal layers for the gate electrode (HK/MG devices). In HK/MG devices, after the type 1 oxide is formed as described above, a high-k layer of insulation material and one or more metal layers are formed above the type 1 oxide layer. In such HK/MG devices, the electrical properties are much more dependent on the inhomogeneous stack of materials—the silicon dioxide (with a relatively lower k value) and the high-k material layer formed there above. The capacitive behavior for the IO devices is dominated by the thicker silicon dioxide gate insulation layer for those devices. Thus, the high voltage devices do not achieve the full benefit of the high-k insulating material, such as significant reduced capacitive thickness at given or even reduced leakage currents.
The present disclosure is directed to various methods of forming I/O (input/output) and standard transistor devices that use high-k insulating materials that may at least reduce or eliminate one or more of the problems identified above.